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2019-02-27riscv: Add SiFive FU540 board supportAnup Patel1-0/+4
2019-02-27riscv: Rename cpu/qemu to cpu/genericAnup Patel1-1/+1
2018-12-18riscv: Enlarge the default SYS_MALLOC_F_LENBin Meng1-0/+3
2018-12-18riscv: qemu: Add platform-specific Kconfig optionsBin Meng1-0/+1
2018-12-18riscv: Implement riscv_get_time() API using rdtime instructionAnup Patel1-0/+8
2018-12-18riscv: Add a SYSCON driver for SiFive's Core Local InterruptorBin Meng1-0/+9
2018-12-18riscv: Introduce a Kconfig option for machine modeAnup Patel1-5/+16
2018-12-18riscv: add Kconfig entries for the code modelLukas Auer1-0/+18
2018-12-05riscv: Add kconfig option to run U-Boot in S-modeAnup Patel1-0/+5
2018-11-26riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen1-0/+6
2018-11-26riscv: add Kconfig entries for the C and A ISA extensionsLukas Auer1-0/+11
2018-11-26riscv: select CONFIG_PHYS_64BIT on RV64I systemsLukas Auer1-0/+1
2018-11-26riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64ILukas Auer1-8/+8
2018-10-03riscv: Add QEMU virt board supportBin Meng1-0/+4
2018-10-03riscv: kconfig: Normalize architecture name spellingBin Meng1-3/+3
2018-05-29riscv: cpu: nx25: Rename as ax25Rick Chen1-3/+3
2018-01-12riscv: Add Kconfig to support RISC-VRick Chen1-0/+42