path: root/arch/riscv
AgeCommit message (Expand)AuthorFilesLines
2019-02-27riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrdAnup Patel1-0/+1
2019-02-27riscv: Add SiFive FU540 board supportAnup Patel1-0/+4
2019-02-27riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systemsAnup Patel1-0/+20
2019-02-27riscv: Add place-holder asm/arch/clk.h for driver compilationAnup Patel1-0/+14
2019-02-27riscv: Add asm/dma-mapping.h for DMA mappingsAnup Patel1-0/+38
2019-02-27riscv: Rename cpu/qemu to cpu/genericAnup Patel5-2/+2
2019-01-15riscv: qemu: define standalone load addressLukas Auer1-1/+1
2019-01-15riscv: remove RISC-V standalone linker scriptLukas Auer1-1/+0
2019-01-15riscv: use invalidate/flush_*cache_range functions in cache.cLukas Auer1-2/+2
2019-01-15riscv: move the AX25-specific implementation of flush_dcache_allLukas Auer2-6/+26
2019-01-15riscv: clarify error message on undefined exceptionsLukas Auer1-1/+2
2018-12-31riscv: bootm: Support booting VxWorksBin Meng1-1/+7
2018-12-18riscv: Remove ae350.dtsBin Meng1-229/+0
2018-12-18riscv: bootm: Change to use boot_hart from global dataBin Meng1-1/+1
2018-12-18riscv: Save boot hart id to the global dataBin Meng3-0/+24
2018-12-18riscv: Adjust the _exit_trap() position to come before handle_trap()Bin Meng1-32/+30
2018-12-18riscv: Return to previous privilege level after trap handlingBin Meng1-8/+0
2018-12-18riscv: Fix context restore before returning from trap handlerBin Meng1-1/+1
2018-12-18riscv: Move trap handler codes to mtrap.SBin Meng3-90/+112
2018-12-18riscv: Do some basic architecture level cpu initializationBin Meng1-1/+26
2018-12-18riscv: Add indirect stringification to csr_xxx opsBin Meng1-7/+9
2018-12-18riscv: Update supports_extension() to use desc from cpu driverBin Meng1-0/+26
2018-12-18riscv: Add exception codes for xcause registerBin Meng1-0/+15
2018-12-18riscv: Add CSR numbersBin Meng1-0/+221
2018-12-18riscv: Remove non-DM version of print_cpuinfo()Bin Meng1-37/+0
2018-12-18riscv: Probe cpus during bootBin Meng2-0/+27
2018-12-18riscv: Enlarge the default SYS_MALLOC_F_LENBin Meng1-0/+3
2018-12-18riscv: qemu: Add platform-specific Kconfig optionsBin Meng2-0/+12
2018-12-18riscv: Implement riscv_get_time() API using rdtime instructionAnup Patel3-0/+47
2018-12-18riscv: Add a SYSCON driver for SiFive's Core Local InterruptorBin Meng5-0/+116
2018-12-18riscv: Introduce a Kconfig option for machine modeAnup Patel1-5/+16
2018-12-18riscv: ax25: Hide the ax25-specific Kconfig optionBin Meng2-11/+18
2018-12-18riscv: qemu: Create a simple-bus driver for the soc nodeBin Meng1-0/+14
2018-12-18riscv: add Kconfig entries for the code modelLukas Auer2-1/+26
2018-12-05riscv: ax25-ae350: Pass dtb address to u-boot with a1 registerRick Chen1-2/+0
2018-12-05riscv: Add kconfig option to run U-Boot in S-modeAnup Patel4-17/+48
2018-12-02riscv: efi: Generate Microsoft PE format compliant imagesBin Meng1-6/+6
2018-11-26riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen9-10/+146
2018-11-26riscv: dts: Add ae350_32.dts for RV32IRick Chen3-1/+458
2018-11-26riscv: dts: Sync to Linux Kernel ae350 dts.Rick Chen1-15/+92
2018-11-26riscv: align bootm implementation with that of other architecturesLukas Auer1-27/+70
2018-11-26riscv: save hart ID and device tree passed by prior boot stageLukas Auer2-2/+16
2018-11-26riscv: do not blindly modify the mstatus CSRLukas Auer1-4/+4
2018-11-26riscv: remove unused labels in start.SLukas Auer1-9/+0
2018-11-26Drop CONFIG_INIT_CRITICALBin Meng1-13/+0
2018-11-26riscv: align mtvec on a 4-byte boundaryLukas Auer1-1/+1
2018-11-26riscv: fix inconsistent use of spaces and tabs in start.SLukas Auer1-161/+161
2018-11-26riscv: implement the invalidate_icache_* functionsLukas Auer1-0/+10
2018-11-26riscv: hang on unhandled exceptionsLukas Auer1-0/+2
2018-11-26riscv: treat undefined exception codes as reservedLukas Auer1-2/+6