summaryrefslogtreecommitdiffstats
path: root/arch/arm/dts/fsl-imx8mq.dtsi
blob: 2394ee2be76eca7d6b1976c6038bb586c3b5bff8 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include "fsl-imx8-ca53.dtsi"
#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/pins-imx8mq.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "fsl,imx8mq";
	interrupt-parent = <&gpc>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &fec1;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		usb0 = &usb3_0;
		usb1 = &usb3_1;
		spi0 = &qspi;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x00000000 0x40000000 0 0xc0000000>;
	};

	gic: interrupt-controller@38800000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
		      <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
			     IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
			     IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
			     IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
			     IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
		clock-frequency = <8333333>;
		interrupt-parent = <&gic>;
	};

	power: power-controller {
		compatible = "fsl,imx8mq-pm-domain";
		num-domains = <11>;
		#power-domain-cells = <1>;
	};

	pwm2: pwm@30670000 {
		compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
		reg = <0x0 0x30670000 0x0 0x10000>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
			 <&clk IMX8MQ_CLK_PWM2_ROOT>;
		clock-names = "ipg", "per";
		#pwm-cells = <2>;
		status = "disabled";
	};

	gpio1: gpio@30200000 {
		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x30200000 0x0 0x10000>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio2: gpio@30210000 {
		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x30210000 0x0 0x10000>;
		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio3: gpio@30220000 {
		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x30220000 0x0 0x10000>;
		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio4: gpio@30230000 {
		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x30230000 0x0 0x10000>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio5: gpio@30240000 {
		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x30240000 0x0 0x10000>;
		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	tmu: tmu@30260000 {
		compatible = "fsl,imx8mq-tmu";
		reg = <0x0 0x30260000 0x0 0x10000>;
		interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
		little-endian;
		u-boot,dm-pre-reloc;
		fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
		fsl,tmu-calibration = <0x00000000 0x00000023
				       0x00000001 0x00000029
				       0x00000002 0x0000002f
				       0x00000003 0x00000035
				       0x00000004 0x0000003d
				       0x00000005 0x00000043
				       0x00000006 0x0000004b
				       0x00000007 0x00000051
				       0x00000008 0x00000057
				       0x00000009 0x0000005f
				       0x0000000a 0x00000067
				       0x0000000b 0x0000006f

				       0x00010000 0x0000001b
				       0x00010001 0x00000023
				       0x00010002 0x0000002b
				       0x00010003 0x00000033
				       0x00010004 0x0000003b
				       0x00010005 0x00000043
				       0x00010006 0x0000004b
				       0x00010007 0x00000055
				       0x00010008 0x0000005d
				       0x00010009 0x00000067
				       0x0001000a 0x00000070

				       0x00020000 0x00000017
				       0x00020001 0x00000023
				       0x00020002 0x0000002d
				       0x00020003 0x00000037
				       0x00020004 0x00000041
				       0x00020005 0x0000004b
				       0x00020006 0x00000057
				       0x00020007 0x00000063
				       0x00020008 0x0000006f

				       0x00030000 0x00000015
				       0x00030001 0x00000021
				       0x00030002 0x0000002d
				       0x00030003 0x00000039
				       0x00030004 0x00000045
				       0x00030005 0x00000053
				       0x00030006 0x0000005f
				       0x00030007 0x00000071>;
		#thermal-sensor-cells =  <0>;
	};

	thermal-zones {
		/* cpu thermal */
		cpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tmu>;
			trips {
				cpu_alert0: trip0 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit0: trip1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
					<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	lcdif: lcdif@30320000 {
		compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
		reg = <0x0 0x30320000 0x0 0x10000>;
		clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>,
			 <&clk IMX8MQ_CLK_DUMMY>,
			 <&clk IMX8MQ_CLK_DUMMY>;
		clock-names = "pix", "axi", "disp_axi";
		assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
		assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
		assigned-clock-rate = <594000000>;
		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	iomuxc: iomuxc@30330000 {
		compatible = "fsl,imx8mq-iomuxc";
		reg = <0x0 0x30330000 0x0 0x10000>;
	};

	gpr: iomuxc-gpr@30340000 {
		compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon";
		reg = <0x0 0x30340000 0x0 0x10000>;
	};

	ocotp: ocotp-ctrl@30350000 {
		compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
		reg = <0x0 0x30350000 0x0 0x10000>;
	};

	anatop: anatop@30360000 {
		compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop",
			"syscon", "simple-bus";
		reg = <0x0 0x30360000 0x0 0x10000>;
		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	};

	clk: ccm@30380000 {
		compatible = "fsl,imx8mq-ccm";
		reg = <0x0 0x30380000 0x0 0x10000>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
		#clock-cells = <1>;
	};

	gpc: gpc@303a0000 {
		compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon";
		reg = <0x0 0x303a0000 0x0 0x10000>;
		interrupt-controller;
		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
	};

	uart1: serial@30860000 {
		compatible = "fsl,imx8mq-uart",
			     "fsl,imx6q-uart", "fsl,imx21-uart";
		reg = <0x0 0x30860000 0x0 0x10000>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
			<&clk IMX8MQ_CLK_UART1_ROOT>;
		clock-names = "ipg", "per";
		interrupt-parent = <&gpc>;
		status = "disabled";
	};

	uart3: serial@30880000 {
		compatible = "fsl,imx8mq-uart",
			     "fsl,imx6q-uart", "fsl,imx21-uart";
		reg = <0x0 0x30880000 0x0 0x10000>;
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
			<&clk IMX8MQ_CLK_UART3_ROOT>;
		clock-names = "ipg", "per";
		dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uart2: serial@30890000 {
		compatible = "fsl,imx8mq-uart",
			     "fsl,imx6q-uart", "fsl,imx21-uart";
		reg = <0x0 0x30890000 0x0 0x10000>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
			<&clk IMX8MQ_CLK_UART2_ROOT>;
		clock-names = "ipg", "per";
		dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uart4: serial@30a60000 {
		compatible = "fsl,imx8mq-uart",
			     "fsl,imx6q-uart", "fsl,imx21-uart";
		reg = <0x0 0x30a60000 0x0 0x10000>;
		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
			<&clk IMX8MQ_CLK_UART4_ROOT>;
		clock-names = "ipg", "per";
		dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	usb3_phy0: phy@381f0040 {
		compatible = "fsl,imx8mq-usb-phy";
		#phy-cells = <1>;
		reg = <0x0 0x381f0040 0x0 0x40>;
		clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
		clock-names = "usb_phy_root_clk";
		assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>;
		assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
		assigned-clock-rates = <100000000>;
		status = "disabled";
       };

	usb3_0: usb@38100000 {
		compatible = "fsl, imx8mq-dwc3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
		clock-names = "usb1_ctrl_root_clk";
		assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>,
				<&clk IMX8MQ_CLK_USB_CORE_REF_SRC>;
		assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
					<&clk IMX8MQ_SYS1_PLL_100M>;
		assigned-clock-rates = <500000000>, <100000000>;
		status = "disabled";

		usb_dwc3_0: dwc3 {
			compatible = "snps,dwc3";
			reg = <0x0 0x38100000 0x0 0x10000>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gpc>;
			phys = <&usb3_phy0 0>, <&usb3_phy0 1>;
			phy-names = "usb2-phy", "usb3-phy";
			power-domains = <&power 2>;
			snps,power-down-scale = <2>;
			snps,dis_u2_susphy_quirk;
			status = "disabled";
		};
	};

	usb3_phy1: phy@382f0040 {
		compatible = "fsl,imx8mq-usb-phy";
		#phy-cells = <1>;
		reg = <0x0 0x382f0040 0x0 0x40>;
		clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
		clock-names = "usb_phy_root_clk";
		assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>;
		assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
		assigned-clock-rates = <100000000>;
		status = "disabled";
       };

	usb3_1: usb@38200000 {
		compatible = "fsl, imx8mq-dwc3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
		clock-names = "usb2_ctrl_root_clk";
		assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>,
				<&clk IMX8MQ_CLK_USB_CORE_REF_SRC>;
		assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
					<&clk IMX8MQ_SYS1_PLL_100M>;
		assigned-clock-rates = <500000000>, <100000000>;
		status = "disabled";

		usb_dwc3_1: dwc3 {
			compatible = "snps,dwc3";
			reg = <0x0 0x38200000 0x0 0x10000>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gpc>;
			phys = <&usb3_phy1 0>, <&usb3_phy1 1>;
			phy-names = "usb2-phy", "usb3-phy";
			power-domains = <&power 3>;
			snps,power-down-scale = <2>;
			snps,dis_u2_susphy_quirk;
			status = "disabled";
		};
	};

	usdhc1: usdhc@30b40000 {
		compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
		reg = <0x0 0x30b40000 0x0 0x10000>;
		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_DUMMY>,
			<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
			<&clk IMX8MQ_CLK_USDHC1_ROOT>;
		clock-names = "ipg", "ahb", "per";
		assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
		assigned-clock-rates = <400000000>;
		fsl,tuning-start-tap = <20>;
		fsl,tuning-step= <2>;
		bus-width = <4>;
		status = "disabled";
	};

	usdhc2: usdhc@30b50000 {
		compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
		reg = <0x0 0x30b50000 0x0 0x10000>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_DUMMY>,
			<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
			<&clk IMX8MQ_CLK_USDHC2_ROOT>;
		clock-names = "ipg", "ahb", "per";
		fsl,tuning-start-tap = <20>;
		fsl,tuning-step= <2>;
		bus-width = <4>;
		status = "disabled";
	};

	sdma1: sdma@30bd0000 {
		compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
		reg = <0x0 0x30bd0000 0x0 0x10000>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
			<&clk IMX8MQ_CLK_SDMA1_ROOT>;
		clock-names = "ipg", "ahb";
		#dma-cells = <3>;
		fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
		status = "okay";
	};

	sdma2: sdma@302c0000 {
		compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
		reg = <0x0 0x302c0000 0x0 0x10000>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
			<&clk IMX8MQ_CLK_SDMA2_ROOT>;
		clock-names = "ipg", "ahb";
		#dma-cells = <3>;
		fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
		status = "okay";
	};

	fec1: ethernet@30be0000 {
		compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
		reg = <0x0 0x30be0000 0x0 0x10000>;
		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
			<&clk IMX8MQ_CLK_ENET1_ROOT>,
			<&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
			<&clk IMX8MQ_CLK_ENET_REF_DIV>,
			<&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
		clock-names = "ipg", "ahb", "ptp",
			"enet_clk_ref", "enet_out";
		assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
				  <&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
				  <&clk IMX8MQ_CLK_ENET_REF_SRC>,
				  <&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
		assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
					 <&clk IMX8MQ_SYS2_PLL_100M>,
					 <&clk IMX8MQ_SYS2_PLL_125M>;
		assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
		stop-mode = <&gpr 0x10 3>;
		fsl,num-tx-queues=<3>;
		fsl,num-rx-queues=<3>;
		fsl,wakeup_irq = <2>;
		status = "disabled";
	};

	imx_ion {
		compatible = "fsl,mxc-ion";
		fsl,heap-id = <0>;
	};

	i2c1: i2c@30a20000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx21-i2c";
		reg = <0x0 0x30a20000 0x0 0x10000>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
		status = "disabled";
	};

	i2c2: i2c@30a30000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx21-i2c";
		reg = <0x0 0x30a30000 0x0 0x10000>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
		status = "disabled";
	};

	i2c3: i2c@30a40000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx21-i2c";
		reg = <0x0 0x30a40000 0x0 0x10000>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
		status = "disabled";
	};

	i2c4: i2c@30a50000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx21-i2c";
		reg = <0x0 0x30a50000 0x0 0x10000>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
		status = "disabled";
	};

	wdog1: wdog@30280000 {
			compatible = "fsl,imx21-wdt";
			reg = <0 0x30280000 0 0x10000>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
			status = "disabled";
	};

	wdog2: wdog@30290000 {
			compatible = "fsl,imx21-wdt";
			reg = <0 0x30290000 0 0x10000>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
			status = "disabled";
	};

	wdog3: wdog@302a0000 {
			compatible = "fsl,imx21-wdt";
			reg = <0 0x302a0000 0 0x10000>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
			status = "disabled";
	};

	dma_cap: dma_cap {
		compatible = "dma-capability";
		only-dma-mask32 = <1>;
	};

	qspi: qspi@30bb0000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx7d-qspi";
		reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
		reg-names = "QuadSPI", "QuadSPI-memory";
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
		<&clk IMX8MQ_CLK_QSPI_ROOT>;
		clock-names = "qspi_en", "qspi";
		status = "disabled";
	};

	dma_apbh: dma-apbh@33000000 {
		compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
		reg = <0 0x33000000 0 0x2000>;
		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
		#dma-cells = <1>;
		dma-channels = <4>;
		clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
	};

	gpmi: gpmi-nand@33002000{
		compatible = "fsl,imx7d-gpmi-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0 0x33002000 0 0x2000>, <0 0x33004000 0 0x4000>;
		reg-names = "gpmi-nand", "bch";
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "bch";
		clocks = <&clk IMX8MQ_CLK_RAWNAND_ROOT>,
			<&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
		clock-names = "gpmi_io", "gpmi_bch_apb";
		dmas = <&dma_apbh 0>;
		dma-names = "rx-tx";
		status = "disabled";
	};
};

&A53_0 {
	#cooling-cells = <2>;
};